Many electronic devices operate in a synchronous manner in which the timing of signals in the device are controlled by a clock signal. The transitions of the clock signal occur at substantially the same time throughout the circuit, thereby ensuring that signals coupled or created responsive to the transitions of the clock signal are properly synchronized to each other.
Although synchronism between signals can be maintained when the same clock signal, or clock signals derived from the same clock signal, are used throughout a circuit. It is substantially more difficult to properly synchronize signals coupled from one electronic device to another when the electronic devices operate in different clock domains defined by different clock signals.
With reference to FIG. 1, a first electronic device 10 receives a signal S.sub.i and a clock signal CLKA. The electronic device outputs a signal S.sub.2 responsive to the input signal S.sub.i and transitions of the clock signal CLKA. The signal S.sub.2 is coupled to the input of a second electronic device 12 through a line 14. The second electronic device 12 also receives a second clock signal CLKB. The second clock signal CLKB may have a phase that is different from the phase of the first clock signal CLKA, and it may even have a frequency that is different from the frequency of the first clock signal CLKA. The problem encountered when coupling the signal S.sub.2 from the output of the first device 10 to the input of the second device 12 is illustrated in FIG. 2.
The clock signal CLKA for the first electronic device 10 is shown in FIG. 2A, and the input signal S.sub.i is shown in FIG. 2B as going high at time t.sub.0. By way of example, the first electronic device 10 simply performs a logical AND function of the input signal S.sub.i and the clock signal CLKA to generate the signal S.sub.2. The signal S.sub.2 is shown in FIG. 2C with exponentially rising and falling edges because of the capacitive loading on the line 14 coupling the first electronic device 10 to the second electronic device 12.
An example of a clock signal CLKB.sub.1 having a first phase is illustrated in FIG. 2D. As shown by comparing FIG. 2A with FIG. 2D, the clock signal CLKA for the first electronic device 10 lags the clock signal CLKB.sub.1 for the second electronic device 12. By way of example, it is assumed that the second electronic device 14 simply functions to clock the signal S.sub.2 (FIG. 2C) on either the rising edge of the clock signal CLKB.sub.1 (FIG. 2F) or the falling edge of the clock signal CLKB.sub.1 (FIG. 2G). As shown in FIG. 2F, the second electronic device 12 is incapable of detecting the signal S.sub.2 when the device 12 is clocked on the rising edge of CLKB.sub.1 because the signal S.sub.2 is not present at the input to the electronic device 12 on the rising edge of CLKB.sub.1. However, as shown in FIG. 2G, the second electronic device 14 is able to detect the signal S.sub.2 if the electronic device 12 clocks the signal S.sub.2 on the falling edge of the clock signal CLKB.sub.1. Thus, the second electronic device 12 can function with the first electronic device 10 despite having different clock domains, but only as long as the clock signal CLKB.sub.1 leads the clock signal CLKA. If the electronic device 12 clocks the signal S.sub.2 on the falling edge of CLKB.sub.1, it will not be able to detect the signal S.sub.2 if the clock signal CLKB lags the clock signal CLKA.
An example of a clock signal CLKB.sub.2 that lags the clock signal CLKA is illustrated in FIG. 2E. The first clock signal CLKA is considered to lag the second clock signal CLKB if any transition of the first clock signal CLKA occurs more than 0 degrees and less than 180 degrees after the corresponding transition of the second clock signal CLKB. The first clock signal CLKA is considered to leasd the second clock signal CLKB if any transition of the first clock signal CLKA occurs more than 180 degrees and less than 0 degrees after the corresponding transition of the second clock signal CLKB. Again, it is first assumed that the second electronic device 12 functions to clock the signal S.sub.2 on the rising edge of the clock signal CLKB.sub.2 (FIG. 2H) or the falling edge of the clock signal CLKB.sub.2 (FIG. 2I). As shown in FIG. 2H, the second electronic device 12 is able to detect the signal S.sub.2 if the electronic device 12 clocks the signal S.sub.2 on the rising edge of the clock signal CLKB.sub.2. However, as shown in FIG. 2I, the second electronic device 12 is incapable of detecting the signal S.sub.2 if the electronic device 12 clocks the signal on the falling edge of the clock signal CLKB.sub.2 because the signal S.sub.2 is not present at the input to the electronic device 12 on the falling edge of the clock signal CLKB.sub.2.
It will be apparent from the above discussion that the second electronic device 12 is able to detect the signal S.sub.2 generated by the first electronic device 10 as long as either the second clock signal CLKB leads the first clock signal CLKA and the second electronic device 12 clocks the signal S.sub.2 on the falling edge of CLKB, or the second clock signal CLKB lags the first clock signal and the second electronic device 12 clocks the signal S.sub.2 on the rising edge of CLKB. However, because the first and second electronic devices 10, 12, respectively, are operating in different clock domains, the phase relationship between CLKA and CLKB can change. Therefore, if the choice is made to make the second electronic device 12 clock the signal S.sub.2 on the falling edge of CLKB, it is possible for the clock signal CLKB to lag the first clock signal CLKA. As explained above, the second electronic device 12 will be unable to detect the signal S.sub.2 under these conditions. Similarly, if the choice is made for the second electronic device 12 to clock the signal S.sub.2 on the rising edge of CLKB, it is possible for the clock signal CLKB to lead the first clock signal CLKA. Again, the second electronic device 12 will be unable to detect the signal S.sub.2.
A more concrete example of the problem illustrated FIGS. 1 and 2 is exemplified by a memory device 20 shown in FIG. 3. The memory device 20 illustrated in FIG. 3 is a packetized dynamic random access memory ("DRAM") having an architecture known as SyncLink. However, the problem may also exist to varying degrees with other types of memory devices, such as synchronous DRAMs. The packetized memory device 20 is shown in somewhat generalized form because the specific structure of the memory device 20 is somewhat peripheral to the inventions described herein. However, packetized memory devices 20 are explained in greater detail in the U.S. patent applications Ser. No. 08/877,191 and 08/874,690.626 to Troy A. Manning which are incorporated herein by reference.
The memory device 20 includes a controller 22 that receives a command packet CA, generally containing several multi-bit packet words, a flag signal F indicating the start are a command packet, and a command clock CMDCLK synchronized to the packet words. The command packet CA includes both memory commands, such as read, write, etc., and bank, row and column address information, as well as other information used to initialize or operate the memory device 20.
The memory device 20 also includes a clock generator 24 that receives the command clock CMDCLK as well as control signals from the controller 22. The clock generator 24 produces several clock signals from the command clock CMDCLK, including an internal clock signal ICLK and a read clock signal RCLK. The phase of the internal clock signal ICLK and the phase of the read clock signal RCLK are determined by control signals from the controller 22. The controller 22 uses the internal clock signal ICLK to generate an initiate signal INIT to start the transfer of read data out to the memory device 20 and write data into the memory device 20. The controller 22 also generates a write phase command signal WPHASE that is used in a manner to be explained below.
Address portions of the command packet CA are coupled to address circuitry 28. The address circuitry 28 then applies bank and row addresses to bank/row circuitry 30 and column addresses to column circuitry 32. The structure and operation of this circuitry 30, 32 is well known to one skilled in the art. Basically, the bank/row circuitry 30 selects a memory array 36 or a portion of a memory array 36, and a row of memory cells in that array. The column circuitry 32 selects a column of memory cells in the array, and data is written to or read from the memory cell in the selected row than intersects the selected column.
Data are coupled between an externally accessible data bus terminal DQ and the column circuitry 32 through a data path 40 that includes a read data path 40a and a write data path 40b. The read data path 40a includes a read register 42 and an output buffer 46 that couple read data from the array 36 via the column circuitry 32 to the data bus terminal DQ. The write data path 40b includes an input buffer 50 and a write register 52 that couple write data from the data bus terminal DQ to the array 36 via the column circuitry 32. During a read operation, read data are applied to a data input of the read register 42 and clocked through the read register 42 by the read clock signal RCLK after the initiate signal INIT from the controller 22 has transitioned active high. During a write operation, write data are applied to the write register 52 and clocked through the write register 52 by a clock signal from a phase shift circuit 56 after the initiate signal INIT has transitioned active high. The phase shift circuit 56 generates the clock signal from a data clock signal DCLK applied to the memory device 20 from an external device, such as a memory controller (not shown). The phase of the clock signal applied to the write register 52 relative to the phase of the data clock DCLK is controlled by the phase command signal WPHASE from the controller 22.
In operation, an external device, such as a memory controller, provides a command packet CA to the memory device 20 to set the timing of the read clock RCLK relative to the command clock CMDCLK. Thus, the phase of the read clock RCLK is controlled by the external device. In a similar manner, the phase of the data clock signal DCLK is determined by the external device, such as a memory controller, generating the data clock signal DCLK. In this manner, the external device controls the timing of the memory device 20 applying read data to the external device.
The memory device 20 shown in FIG. 3, when coupled to external devices, such as memory controllers, must operate in two clock domains. The first clock domain is defined by the internal clock signal ICLK, which corresponds to the timing of the control signals from the controller 22. Thus, the functions carried out by the controller 22, such as receiving data from and outputting data to the array 36, and initiating data transfers responsive to the initiate signals INIT, are in the first clock domain. The coupling of data through the read register 42 is in a second clock domain because the coupling of signals through the read register 42 is controlled by the read clock signal RCLK, and the phase of the read clock RCLK is determined by the external device. Similarly, the coupling of signals through the write register 52 is in the second clock domain because the coupling of signals through the write register 52 is controlled by the data clock signal DCLK, and the phase of the data clock signal DCLK is determined by the external device. Operation of the memory device 20 in two clock domains can cause problems of the type explained above with reference to FIGS. 1 and 2. In fact, it is particularly difficult to avoid such problems when operating at the high data rates that are the goal of the SyncLink packetized DRAM.
There is therefore a need to provide a method and apparatus that is capable of coupling signals from a first electronic device to a second electronic device, and to allow first and second electronic devices to operate together, despite the first and second electronic devices being in different clock domains.